1. Field of the Invention
This invention relates to the field of data memories. More particularly, this invention relates to content addressable memories.
2. Description of the Prior Art
It is known to provide content addressable memories of the type illustrated in FIG. 1 of the accompanying drawings. FIG. 1 shows an example of a cache memory 2 including a content addressable memory 4 and an array of cache RAM 6. In operation, an input data word 8 is supplied at the data word input 10 of the content addressable memory. The input data word 8 comprises bits [31:5] of the address location of the data value (data or instruction) being sought. The input data word 8 is passed along the bit lines 12 through the content addressable memory 4 such that it is available to each of the rows of bit storage and comparison cells within the content addressable memory 4. Each row of bit storage and comparison cells compares the input data word with the data word it is storing and, if a match is detected, generates a match signal on a match line. This match signal indicates that the corresponding row within the cache RAM 6 contains the data being sought. The cache RAM 6 contains eight data words and the bits [4:2] in conjunction with a multiplexer 14 are used to select the data word for output from the cache RAM 6.
A discussion of this type of circuit may be found in the book "Principles of CMOS VLSI Design--A Systems Perspective", Second Edition, Neil H E Weste and Kamran Eshraghian, Section 8.3.3, page 589.